Metal oxide semiconductor (MOS) transistors in integrated circuit devices including non-volatile memory devices and logic devices have been scaled down to smaller and smaller dimensions. In non-volatile memory devices, nanocrystals have been proposed as a replacement for conventional floating gates to scale down the thickness of tunnel oxides. In conventional nanocrystal-based non-volatile memory devices, program and erase operations are typically achieved by Fowler-Nordheim (FN) tunneling. However, the fabrication processes for conventional nanocrystal-based non-volatile memory devices may not be compatible with high dielectric constant/metal gate (HK/MG) processes, which are becoming popular for the fabrication of high-density of memory devices. Moreover, conventional nanocrystal-based non-volatile memory devices may suffer from charge loss due to their degradation mechanism. Furthermore, even with the implementation of nanocrystals to reduce the thickness of tunnel oxides, further scaling down of non-volatile memory devices may be limited due to the limitations on device density imposed by nanocrystal processes.